- Manage ASIC project lifecycle, from requirements, design, technical architecture, implementation, testing, acceptance, training and documentation.
- Maintain close monitoring of project progress and report potential risks and challenges in a timely manner with proposed course of actions.
- Determine and manage resources from start to finish with attention to budgetary limitations.
- Build and maintain relationships with external stakeholders.
- Oversee and/or prepare incoming and outgoing project documentation.
- Technical leadership of project team.
- Perform HDL coding, synthesis, verification, timing closure, tapeout for project.
- A Bachelors or Masters Degree in Electrical/Electronics Engineering, Computer Engineering, or relevant fields.
- Minimum 5 years engineering experience in HDL coding, implementation and ASIC tapeout.
- Minimum 3 years of experience in project management or team lead in product development.
- Able to multi-task and manage various project elements simultaneously.
- Strong team leader and individual contributor.
- Good spoken and written communication skills in English.
- Singaporean only.
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R&D ASIC Project Manager - Singapore - SEARCH STAFFING SERVICES PTE. LTD.
Description
Roles & ResponsibilitiesOur client is a leading crytographic technology development firm in Singapore, providing design and development services to its partners and customers. We have the following vacancy for:
R&D ASIC Project Manager (Product Development) - Singaporean only
Responsibilities:
Requirements
Interested applicants, kindly send in a copy of your updated resume in WORD document to stating your current and expected remuneration together with notice period required to current employer.
You can also contact Vincent Low for a confidential discussion at
EA Personnel Registration No: R1324700
Tell employers what skills you haveVHDL
Able To Multitask
HDL
Timing Closure
Technology Development
Project Management
Finish
Technical Architecture
Team Lead
Team Leader
ASIC
Product Development
Technical Leadership
Verilog
