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Technology / Internet
Elvira Febiani

Elvira Febiani

Senior Product Test Engineer


About Elvira Febiani:

Driven by a passion for innovation and excellence, I possess a breadth of technical expertise and project management skills. With a track record of success, I am confident in my ability to deliver outstanding results and showcase my capabilities effectively.

Experienced in end-to-end silicon production with high-level reporting, risk management and low-level solution enablement 


Qualcomm Global Trading Pte Ltd

Senior Product Test Development Engineer                                                           Feb 2022 – Present

  • Promoted to Senior Product Test Engineer
  • Lead a 95-days record post-silicon mobile chipset project execution in enabling test solution across insertions WS, FT, SLT and QA
  • Achieve Product Marketing goals, by 14% of Fmax, through cross-nation correlation
  • Successfully deliver product launch to mass production for OEM enablement, such as Honor, Vivo, Oppo, Xiaomi, and Motorola
  • Drive cost savings and production KPI improvement, such as Yield, up to 99.5%, Test Time, up to 10% from original projected steady state and Retest Rate reduction by 10%
  • Engaged with directors and senior managers for end-to-end planning, high level reporting and risk management

Test Development Engineer                                                                                        Jul 2018 – Jan 2022

  • Maximized production yield, above 99.8%, reduced test cost by 50% within 2 months ahead of schedule.
  • Expertised in productizing analog circuit NPI post-silicon bring up until mass production steady state, within record 100 days
  • Achieved Qualstar Recognition on productivity improvement (up to 75%) with PLL setting script checker, and for knowledge sharing session conducted for automation tool with test program generator
  • Developed ATE Production Test Programs and hardware platforms for commercial and test chips SoC products
  • Managed the balance between design and production goal, such as coverage and test time budget 


Pepperl+Fuchs Asia Pte Ltd
Intern                                                                                                                             Jan 2017 – Jul 2017

Project 1: TPU Filling Scrap Reduction Project

  • Saved scrapped cost up to S$38K annually due to HV test on top 2 product
  • Completed 80% in 5 months, due in end of July 
  • Applied DMAIC tools to determine robust root cause analysis, such as Pareto, Ishikawa and Poka Yoke

Project 2: Silicon Coating Evaluation Project

  • Established and socialized new guideline on silicon coating process within 2 months
  • Experimented and identified golden guide of mixing ratios between silicone and hardener


Nanyang Technological University Singapore                                                        Aug 2014 – Jul 2018

Bachelor of Engineering: Electrical and Electronics Engineering
Grade: Second Upper Class with Honours (Distinction)


Notable Academic Project - NTU EEE Final Year Project                                                                                               

An Advanced Firewall Rules Matching Algorithm (Aug 2017 - May 2018)

  • Published research journal in IEEE Conference on Service Operations and Logistics, and Informatics (SOLI) in July 2018 on this study
  • Remodeled a new algorithm for firewall matching rules with efficiency improvement, by 89%
  • Productized the improvement in C language to build an enhanced firewall for the SCADA network

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