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senthilnathan chidambaram murugan

senthilnathan chidambaram murugan

Digital IC design verification engineer
Bukit Batok New Town

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About senthilnathan chidambaram murugan:

My name is Senthil Nathan. I have 4 years of experience working as design verification engineer in singapore.I have a keen interest in VLSI Design and verification. Having worked on presilicon verification of feature rich ASIC designs at both SOC/IP level, looking forward to learn and experience new things that are emerging in this era. A team player and able to work as a key player in competitive environment. I am currently open to opportunities.

Experience

Realtek Singapore, Design Verification Engineer                                                                                                                                                                                       March 2019 – Present

 

  • Created test plan for various digital IPs based on their respective product specification.
  • Reviewed the test plan with design team and confirmed if any additional requirements/scenarios to be added for the IP.
  • Developed test bench components, test cases and checkers for the SOC/IP level verification.
  • Debugged the test failures and regressed the test cases in RTL simulation to achieve 100% functional coverage.
  • Executed the post layout netlist simulation successfully with different sdf corners to satisfy the verification sign-off.

 

Professional Project 

Ameba Pro2

  • Developed and maintained test bench for IC peripherals like pwm, SGPIO, GPIO, timer and rsa whenever any feature change was updated.
  • Expertise in using BFMs like AXI4, APB4 to communicate with the IP and verified the response from the DUT.
  • Used Verdi tool to debug & find the root cause for any issue and reported the critical issues in the RTL design. 
  • Achieved the target functional and code coverage to ensure complete verification of the IP.
  • Worked on system level interrupt connectivity using immediate assertion.
  • Accomplished successful execution of RTL and post layout netlist simulations required to meet the tape-out criteria.

 

Mercury

  • Prepared test plan and developed test cases for Queue Management module.
  •  Used Verdi tool to debug & find if any packet lost or modified and reported the issues in the RTL design.

 

Mechatronics Lab R&D (NTU) Singapore, Research Associate                                                                                      Aug 2017 – March 2019                                                                                   

 

Smart Crane System                                                                                                                                  

 

  • Developed a Robotic Tower Crane by collecting data from external Sensors and wirelessly (via zigbee, Wi-Fi) transferring the measured sensor data to the overriding Tower Crane control system.
  • Programmed Atmega 328P MCU to acquire the distance data from long range laser sensor and accomplishing wireless transfer of this data through Zigbee. 
  • Published the laser sensor data on ROS (Robot Operating System) using a publisher node written on C++. 

Extracted the slew angle data from the absolute encoder (SSI-SPI interface) by programming Atmega 328P MCU.

Education

Master of Science - Control and Automation (School of EEE)                                                                                                 Jul 2016 – Jul 2017

Nanyang Technological University (NTU), Singapore                                                                                         

Bachelor of Engineering - Electronics and Communication                                                                                                   Jun 2012 - May 2016                                                                                                                                                            

College of Engineering, Guindy, Anna University, India   

 

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