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I have superior communication and organisational skills, excellent performance in problem solving and debugging. Iam a good team worker and open to take up new roles and challenges. I also enjoy learning new things and canadapt new concepts and situation quickly.

- Flash memory design -ESF3 (non-volatile NAND memories)
- Power management for memory cell in READ, WRITE and ERASEmode.
- Experienced in designing LDO, voltage monitor circuit, start-up(for ultra-low power amplifier ), sensing block, standard cells, 4 phasepump, oscillator, pi-model loading, word line driver.
- Experienced in Hspice simulation when designing block level, Fastspice (XA simulation) with full chip level and mote- carlo simulation.
- Understanding of parasitic element (R/L/C) in layout and fabricationprocess (SCA)Check and fix LVS, DRC in layout. Familiar with xRC ofSynopsys and Cadence.
- Owner some projects fixed IR drop, EM violation of power net withusing TOTEM tool.
- SPF, HSPICE format extraction.
- Understanding life time and how to increase life time checking fordevices.
- High voltage device check and optimization. (GIDL effect)
- Using Black box and white box extraction for increasing accuracylevel and speed of simulation in xRC Cadence
-Experienced in logic verification and fixed successfully logic violationis feed back from customers.

- EMIB, PHY design, highspeed IO reach to 2Ghz
- Bi-directional cell (TX, RX function), LDO, comparator, functionalcheck simulation, EM IR check, post-sim, DCD, delay check.
- Liberty, timing lib generation used silicontsmart for AIP andprimetime for CBB level.
- Calibration mode, DDR, SDR, Loop back mode optimization.
- GDS/OASIS file export for StarRC extraction.
- ESD verify and improvement.
- Capacitor check using siliconsmart and simulation.
- Aging, SOAC, RV verification and optimization.
- Improve yield of driver range code.
- Optimize cap loading for IO.
- Deep understanding Finfet process.
- Proficiency with UNIX and CADENCE design environment(Simulation, Schematic entry, SPF extraction).
- PERL and PYTHON script for automation design.
- Co-simulation (digital and analog simulation)
- Model pre-sim to get close with post sim.
- HV(high voltage checking) using for DRC check using maestroenvironment of Cadence.
- HSPICE, FINESIM, XA simulation using UNIX environment andusing PERL, PYTHON for automation running.
- SPECTRE simulation in maestro to check RV, Aging....
- Worked with finfet 5nm TSMC, 10nm Intel process.