SoC Verification Engineer - Singapore - ENVIRODYNAMICS SOLUTIONS PTE. LTD.

    ENVIRODYNAMICS SOLUTIONS PTE. LTD.
    ENVIRODYNAMICS SOLUTIONS PTE. LTD. Singapore

    1 month ago

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    Description
    Roles & Responsibilities

    Responsibilities

    • Designing & deploy verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
    • Perform test plan reviews systematically and execute the plan on-time with high quality.
    • Achieve zero-defect with the best and smartest approach to the large verification space.

    Requirements

    • Bachelor & Master in Electrical Engineering or Computer Engineering
    • At least 10 years of relevant experience.
    • Expertise in Universal Verification Methodology (UVM) processes.
    • Quality-minded, and highly driven for excellence.
    • Excellent team player and good communication skills.
    • Experience in video processing and video analytics is a plus.

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    EnviroDynamics Solutions Pte Ltd (EDS)

    Reg. No: R1324803

    EA License No.: 12C6285

    Tell employers what skills you have

    Video Analytics
    Documentation Skills
    Test Cases
    UVM
    Good Communication Skills
    IP
    SoC
    Video Processing
    Team Lead
    Ethernet
    Flash
    Functional Verification
    ASIC
    Verilog
    Electrical Engineering
    VLSI