- Develop and Review Test Plan based on IC design specification
- Develop constrained-Random verification environment for complex DUT
- Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
- Implement coverage matrix using cover point and assertion
- Create and debug tests for DUT
- Resolve bugs with remote designers
- Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
- Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
- Strong understanding of verification process from test plan to coverage completion
- Strong communication and Analytical skills
- Understanding of HDL (Verilog, VHDL)
- Experience with designing with FPGA using Vivado is a plus
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Design Engineer
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design engineer
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design engineer
Found in: Talent SG 2A C2 - 3 days ago
STARBURST ENGINEERING PTE LTD SingaporeRoles & Responsibilities · Job requirement and responsibilities: · 1. Prepare and develop Engineering and design drawings · 2. Prepare and develop Structural modeling and detailing · 3. Coordination with the other departments. · 4. Collaboration with clients, architects, engineer ...
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design engineer
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Design Engineer
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Sr /IC Design Engineer (Design Verification) - Singapur, Singapore - ETHOS SEARCH ASSOCIATES PTE. LTD.
Description
Roles & ResponsibilitiesJob Descriptions
Requirements
Ethos Search Associates Pte. Ltd.
EA Licence No: 13C6655
EA Reg No: R Rose
Invention
Analytical Skills
Digital IC Design
EDA
UVM
RTL Design
IP
FPGA
SoC
SystemVerilog
Flash
Computer Architecture
Functional Verification
ASIC
Debugging
IC
Verilog
VLSI