Jobs

    PQE Yield Engineer - Singapur, Singapore - Micron

    Micron
    Micron Singapur, Singapore

    1 week ago

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    Description

    Our vision is to transform how the world uses information to enrich life for all.

    Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

    JR47796 PQE Yield Engineer (Evergreen)

    Responsibilities:

  • Responsible for new product startup and yield improvement
  • Support design verification and in-depth circuit of new products using CAD tools and Verilog simulations
  • Work with the wafer fab process/integration group to address process-related defects affecting product yield
  • Perform bench validation to support product characterization and electrical failure analysis
  • Perform electrical failure analysis to understand the root cause of the different yield issues and make recommendations for improvement to PE and Design.
  • Identify design marginalities and recommend design fix for circuit-related problems
  • Perform data analysis through analysis/statistic tools, summarize, present and publish data/result to all associated groups.
  • Design and run DOE to drive yield improvement activities.

    • C1+ Yield Engineering:

  • Lead Yield enhancement for C1+, including yield monitoring, performance to plan, drive C1+ yield program, coordinate FAB/PE/PYE effort to resolve process/device/test related yield issues.
  • Assess C1+ cumulative yield and return on investment, reference PTS flow/yield to influence C1+ test flow to minimize C1+ flow overkill and optimize C1+ coverage & quality. Work with PE on C1+ test/device optimization.
  • Bench characterization/EFA on C1+ failures, propose solution for baseline improvement.
  • High Stack yield enhancement. work with PYE/PE to monitor high stack yield performance to plan, resolve high stack yield challenge, coordinate FAB/PE/PYE effort to resolve process/device/test related yield issues.
  • Work and propose strategy to improve high stack yield such as additional C1/C1+ coverage or material channeling.

    • Requirements:

  • Bachelor's/Master's Degree in Electrical/Electronic Engineering, Microelectronic background is preferred.
  • Experience in yield analysis/EFA will be added advantage in consideration.
  • Good understanding of CMOS device physics is an added advantage
  • Excellent problem-solving and analytical skills.
  • Knowledge of CMOS circuit design and CAD/Simulation is an added advantage
  • Knowledge of NAND devices operations is an added advantage
  • Understanding of C1+ Probe Test flow and test methodology including array operation, customer feature and specification is an added advantage.
  • Willing to work flexible hours that overlap with different time zones, or nights and weekends if necessary.

    • Working Location

  • 1, North Coast Drive, Singapore 757432
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