- Responsible for pre-silicon RTL coding of block, subsystem and top level SOC Integration
- Develop robust and reusable Code and ensure VHDL or Verilog implementation enables readiness for Verification, Synthesis, DfT and Low Power Insertion
- Develop reusable RTL Code, using Generic and Modular Coding Styl
- Contribute to verification plan from specification and in coordination with architects
- Collaborate on Timing constraints, Testability and Insertion of Low Power Structure such as Power gating, Isolation and Retention Sequential Elements
- Own Linting, CDC, RDC and collaborate with Verification Team and Physical Design
- Co-work with Architecture/ Design/Validation/SW teams. Own cross functional micro-architecture and implementation and drive issues to closure
- Bachelor Degree or Master's in Electronics Engineering with 8 to 10 years and above of related working experience
- Expert in VHDL and Verilog Coding, Front End Design using best-in-class methodology and Micro-architecture
- Good experience in developing Multi-Million gates IP and integrated heterogenous complex SoC, including Analog and Mixed Signal IP
- Participated in Micro-architecture Specification
- Familiar with Hardware-Software Partitioning, Multi-CPU and Multi-Core Architecture
- Deep knowledge and understanding of NoC and multi-layer complex Interconnect Systems
- Solid verification skills in problem solving, constrained random testing and debugging
- Deep understanding of design architecture and possess meticulous attention to details
- Expertise with Code Linting tools and Static Code checker such as Spyglass, Real Intent, etc
- Expertise in IP-XACT, Connectivity Checks, Register Interfaces and RTL Assembly Tools
- Programming experience in C/C++/assembly/SVA
- Good experience in working with ARM and ARM Eco-system, AXI, AHB, SERDES systems, communication peripherals(UART, I2C, SPI) and power management
- Experience in WiFi/DOCSIS/Ethernet/DSP/DDR is a plus
- Setup Automated regressions environment and in general automate repetitive verification tasks to enhance productivity
- Strong team player and communicator
- Current salary, including AWS or Variable Bonus
- Expected salary
- Availability
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6 days ago
Description
Roles & ResponsibilitiesJob Responsibilities:-
Job Requirements:-
Location: Next to Bendemeer MRT
Interested candidates may submit detailed CV with the following info:-
VHDL
Analog
SERDES
ARM
Mixed Signal
Power Management
NOC
C/C++
RTL Design
IP
SoC
Engineering Design
DSP
Team Player
UART
DOCSIS
Debugging
IC
Physical Design
Verilog
 PTE. LTD.&v=024){kind=logo}
