- Expert knowledge of DFT architecture on complex Design with multiple clock domains.
- Experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, Bridging fault and Small delay defects .
- Experience in industry standard DFT tools - Mentor Tessent suite, Synopsys DFT compiler.
- Expert knowledge on scan coverage improvement and Test time reduction.
- Experience with standard JTAG protocol and Boundary scan.
- Should have participated in successful tapeouts of DSM SoC/ASIC chips at 40nm or below and achieved test targets.
- Experience working with cross functional global teams
- Experience in Low-Power DFT requirements.
- Experience in Low-Power MBIST architectures and Memory testing.
- Experience of working with Advantest, Teradyne testers.
- Experience in DFT related RTL integration.
- Excellent debugging and Scripting skills.
- Excellent communication and analytical skills
- Mentoring skills
- Exceptional problem-solving skills
- Equity Rewards (RSUs)
- Employee Stock Purchase Plan (ESPP)
- Insurance plans with Outpatient cover
- Flexible work policy
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DFT Lead Engineer - Singapur, Singapore - Silicon Labs
Description
We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.
Responsibilities :
Person will be responsible for DFT Architecture including JTAG functionality, boundary scan, hierarchical scan, at- speed testing, I/ O testing requirements, MBIST and Repair, implement test logic for analog macros. Person should also be responsible to develop firmware driven cost-effective test strategies methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on ATE. Person should be capable of generate and debug DFT patterns on tester.
Experience Level: 5-8 years in Industry
Education Requirements: B.Tech/M.Tech in ECE, EEE
Minimum Qualifications:
Preferred Qualifications:
Benefits & Perks :
Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.
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