Technical Director, Physical Design - SG - Singapore

The Physical Design Engineer will be responsible for high-performance block implementation , perform block level floor planning , power grid implementation, APR placement, timing optimisation , CTS and routing . · At least 3 years of hands-on experience in digital-physical design ...

Responsibility for digital circuit physical implementation and PV/PI signoff; perform full-chip STA signoff and conduct SPICE simulation for critical timing paths. · ...

We are looking for a sharp hands-on engineer to join our backend team. In this role you will focus on block-level execution.You will move beyond standard nodes to work on ultra-deep submicron geometries receiving mentorship from senior leads to master the flow. · ...

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. · The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) ...

Job Description · MediaTek's Physical Design team is responsible for implementing top · quality digital backend design · for our advanced process chips, which have billions of transistors. · [What's in it for you?] Responsible for physical design and development of a variety of S ...

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. · ...

Responsibility · 1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/ ...

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the so ...

Silicon Labs is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. · ...

Responsibility · Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; · Develop, optimize, and maintain PR/PV ...

About Marvell · Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. · At Marvell, you can affec ...

We are seeking a highly skilled and experienced Senior Physical Chip Design Engineer to lead the development and optimization of low-power, high-performance chip design processes. This role requires a deep understanding of advanced semiconductor technologies and the proven abilit ...

· Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Conne ...

About Marvell · Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. · At Marvell, you can affec ...

Physical Design Engineer (Digital IC) · Reporting to: General Manager  · ​​​​​​The client is a new startup chip design service company in Singapore. The company is headquartered in Singapore. The company's main business is chip design services and chip mass production business,  ...

Maxlinear is seeking a Principal Physical Design Engineer to join our team in Singapore. Be part of a SoC LPS team dealing with complex Communication ICs (wifi, router, ethernet ) in 7nm and below. · ...

Job Description · Lead the physical design of automotive‑grade SoC chips, driving the complete RTL‑to‑GDS flow while ensuring full compliance with functional safety standards (ISO · Work closely with the front‑end design team to support architecture analysis, logic synthesis, an ...

We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node. · You will take ownership of physical implementation from RTL to GDSII, ensure timing and power closur ...

Job Description · [What you will do] IC physical design of 12nm/6nm/4nm and below world leading advanced process chip, from RTL to GDS. · Block owner, take block of 2~3 Million instances, working on Synthesis/APR (auto place and route)/Signoff · Block coordinator role for more th ...

Job Description · Lead the physical design of automotive‑grade SoC chips, driving the complete RTL‑to‑GDS flow while ensuring full compliance with functional safety standards (ISO · Work closely with the front‑end design team to support architecture analysis, logic synthesis, an ...