- Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.
- Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff
- Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.
- TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout
- Bachelor/Master Degree in Electrical/Computer Engineer.
- Experience in physical design with tape-outs.
- Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus.
- Good in script programming with Perl, TCL/TK or other languages.
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SOC Physical Design Engineer x6 - Singapore - ALPSOFT TECHNOLOGIES PTE. LTD.
Description
Roles & ResponsibilitiesResponsibilities:
Requirements:
Interested candidate kindly forward your *Updated resume (word doc format) to
Tell employers what skills you havePerl
Static Timing Analysis
Timing Closure
Modeling
Analog
Floorplanning
Scripting
IP
TCLTK
Python
Cadence
DFT
Benchmarking
IC
Physical Design
Electrical Engineering
Layout