Mei Yuet Cheong

I am a fast learner and willing to take on challenges. In order to pursue a career as a successful DFT engineer, I am open to any opportunity that can help me develop my DFT related professional skills.

1. Synthesis / DFT implementation Engineer

• Perform RTL synthesis, DFT scan insertion and generate optimized Gate Level Netlist for Timing, Area and Power. Worked with designers to debug on the timing/area/congestion related issues.
• Run ATPG coverage and improve the coverage for stuck at faults and transition faults.
• Perform Formal Verification checks between RTL and Gate level netlist.
• Perform Quality Analysis check on the final netlist with scan inserted such as STA, CLP, LEC, DFTC QA before releasing the netlist deliverables to top/PD.

     2. SOC Design Engineer (DFT MBIST)

• Perform RTL insertion for DFx MBIST using the TESSENT Mentor
  tool on Intel next-generation SoC and PCH chipset products.
• Involved in RTL quality check such as LINTING and FEV.
• Generate MBIST and BISR test patterns in IP TAP and full chip level.
• Enable MBIST and BISR tests in OVM/UVM test environment.
• Perform MBIST and BISR feature verification and test debug in SOC
  full chip level.
• Develop and release MBIST test programs to the manufacturing
  team in a timely manner.
• Collaborate with the post-silicon manufacturing team to enable
  MBIST test content capability for silicon testing and support them
  in post-silicon debugging during silicon power on.
• Develop functional ECO tcl scripts to modify the gate level netlist
  of a design.
• Drive continuous process/flow improvement in the MBIST team
  domain through python automation scripts to increase work
  efficiency and productivity.
• Collaborate with tool's owner team for tools issue feedback and
  enhancement.

Graduated with Bachelor Degree Electronics Engineer (HONS)